PROTOTIPE PENGALI PADA SPARTAN-2 FPGA SEBAGAI
PENDUKUNG TAPIS DIGITAL PADA RADIO DETECTION
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Institusion
INSTITUT TEKNOLOGI DIRGANTARA ADISUTJIPTO
Author
Setiawan, Adi
Subject
T Technology (General)
Datestamp
2024-07-11 02:49:13
Abstract :
A multiplier is one of the most important parts of a device that can affect device performance. So, high speed and efficient multiplier systems are important factors for designers of microprocessor devices, digital microcontrollers and others. As is known, multiplication operations are not difficult to do in decimal numbers. But, to do operations in binary numbers (which are used in digital systems) is a very complex operation. Significant acceleration in time calculation can be achieved by setting intensively the calculation process task using hardware and by utilizing parallel processes in the algorithm. Field Programmable Gate Arrays (FPGAs) have emerged as the preferred platform for efficient hardware implementation. FPGA allows a high level of parallelism so that it can increase the embedded resources available on the FPGA. FPGA benefits from hardware speed and software flexibility. This thesis provides an analysis of multiplier algorithms the results of LPF digital filter implementation output using the hamming window method with IC chip design in xillinx 10.1 software. This method is used to design IC multiplier chips to support the LPF digital filter, so that coefficients can be determined which will later be used in the multiplier LPF digital filter implementation algorithm. Based on this study, the results of the observation show that the LPF FIR digital 8 bit multiplier algorithm using the hamming window method can be implemented on the FPGA and the output filter is in accordance with the specifications of the design results. But there is an error between the results of the theory and the simulation and implementation of the tool. The biggest error is 52.32% at the 4th coefficient (0.01748) and the smallest error is 0.72% at the 1st coefficient (0.31478).
A multiplier is one of the most important parts of a device that can affect device performance. So, high speed and efficient multiplier systems are important factors for designers of microprocessor devices, digital microcontrollers and others. As is known, multiplication operations are not difficult to do in decimal numbers. But, to do operations in binary numbers (which are used in digital systems) is a very complex operation. Significant acceleration in time calculation can be achieved by setting intensively the calculation process task using hardware and by utilizing parallel processes in the algorithm. Field Programmable Gate Arrays (FPGAs) have emerged as the preferred platform for efficient hardware implementation. FPGA allows a high level of parallelism so that it can increase the embedded resources available on the FPGA. FPGA benefits from hardware speed and software flexibility. This thesis provides an analysis of multiplier algorithms the results of LPF digital filter implementation output using the hamming window method with IC chip design in xillinx 10.1 software. This method is used to design IC multiplier chips to support the LPF digital filter, so that coefficients can be determined which will later be used in the multiplier LPF digital filter implementation algorithm. Based on this study, the results of the observation show that the LPF FIR digital 8 bit multiplier algorithm using the hamming window method can be implemented on the FPGA and the output filter is in accordance with the specifications of the design results. But there is an error between the results of the theory and the simulation and implementation of the tool. The biggest error is 52.32% at the 4th coefficient (0.01748) and the smallest error is 0.72% at the 1st coefficient (0.31478).
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